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HY29LV320
32 Mbit (2M x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
- Read, program and erase operations from 2.7 to 3.6 volts - Ideal for battery-powered applications High Performance - 70, 80, 90 and 120 ns access time versions for full voltage range operation Ultra-low Power Consumption (Typical/ Maximum Values) - Automatic sleep/standby current: 0.5/5.0 A - Read current: 9/16 mA (@ 5 MHz) - Program/erase current: 20/30 mA Top and Bottom Boot Block Versions - Provide one 8 KW, two 4 KW, one 16 KW and sixty-three 32 KW sectors Secured Sector - An extra 128-word, factory-lockable sector available for an Electronic Serial Number and/or additional secured data Sector Protection - Allows locking of a sector or sectors to prevent program or erase operations within that sector - Temporary Sector Unprotect allows changes in locked sectors Fast Program and Erase Times (typicals) - Sector erase time: 0.5 sec per sector - Chip erase time: 32 sec - Word program time: 11 s - Accelerated program time per word: 7 s Automatic Erase Algorithm Preprograms and Erases Any Combination of Sectors or the Entire Chip Automatic Program Algorithm Writes and Verifies Data at Specified Addresses Compliant With Common Flash Memory Interface (CFI) Specification - Flash device parameters stored directly on the device - Allows software driver to identify and use a variety of current and future Flash products Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
- Pinout and software compatible with single-power supply Flash devices - Superior inadvertent write protection Data# Polling and Toggle Bits - Provide software confirmation of completion of program and erase operations Ready/Busy (RY/BY#) Pin - Provides hardware confirmation of completion of program and erase operations Write Protect Function (WP#/ACC pin) - Allows hardware protection of the first or last 32 KW of the array, regardless of sector protect status Acceleration Function (WP#/ACC pin) - Provides accelerated program times Erase Suspend/Erase Resume - Suspends an erase operation to allow reading data from, or programming data to, a sector that is not being erased - Erase Resume can then be invoked to complete suspended erasure Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data Space Efficient Packaging - 48-pin TSOP and 63-ball FBGA packages
n n
n
n
n n
n
n n
n
n n
n
LOGIC DIAGRAM
n n n
21 A[20:0] CE# OE# WE# RESET# WP#/ACC RY/BY# DQ[15:0]
16
n
Revision 1.3, May 2002
HY29LV320
GENERAL DESCRIPTION The HY29LV320 is a 32 Mbit, 3 volt-only CMOS Flash memory organized as 2,097,152 (2M) words. The device is available in 48-pin TSOP and 63ball FBGA packages. Word-wide data (x16) appears on DQ[15:0]. The HY29LV320 can be programmed and erased in-system with a single 3 volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage VPP power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as fast as 70ns over the full operating voltage range of 2.7 - 3.6 volts are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. To eliminate bus contention, the HY29LV320 has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a word at a time by executing the four-cycle Program Command write sequence. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Faster programming times are achieved by placing the HY29LV320 in the Unlock Bypass mode, which requires only two write cycles to program data instead of four. The HY29LV320 features a sector architecture and is offered in two versions: n HY29LV320B - a device with boot-sector architecture with the boot sectors at the bottom of the address range, containing one 8KW, two 4KW, one 16KW and sixty-three 32KW sectors. n HY29LV320T - a device with boot-sector architecture with the boot sectors at the top of the address range, containing one 8KW, two 4KW, one 16KW and sixty-three 32KW sectors. The HY29LV320's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents
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of other sectors. Device erasure is initiated by executing the Erase Command sequence. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Sectors are arranged into designated groups for purposes of protection and unprotection. Sector Group Protection optionally disables both program and erase operations in any combination of the sector groups of the memory array, while Temporary Sector Group Unprotect allows in-system erasure and code changes in previously protected sector groups. Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory. Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. After a program or erase cycle has been completed, or after assertion of the RESET# pin (which terminates any operation in progress), the device is ready to read data or to accept another command. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Secured Sector is an extra 128 word sector capable of being permanently locked at the factory or by customers. The Secured Indicator Bit (accessed via the Electronic ID mode) is permanently set to a `1' if the part is factory locked, and permanently set to a `0' if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Secured Sector may store a secure, random 8-word ESN (Electronic Serial Number), customer code programmed at the factory, or both. Customer Lockr1.3/May 02
HY29LV320
able parts may utilize the Secured Sector as bonus space, reading and writing like any other Flash sector, or may permanently lock their own code there. The WP#/ACC pin provides two functions. The Write Protect function provides a hardware method of protecting the boot sectors without using a high voltage. The Accelerate function speeds up programming operations, and is intended primarily to allow faster manufacturing throughput. Two power-saving features are embodied in the HY29LV320. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The host can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Common Flash Memory Interface (CFI) To make Flash memories interchangeable and to encourage adoption of new Flash technologies, major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and configurations in which all necessary Flash device parameters are stored directly on the device. Parameters stored include memory size, byte/word configuration, sector configuration, necessary voltages and timing information. This allows one set of software drivers to identify and use a variety of different, current and future Flash products. The standard which details the software interface necessary to access the device to identify it and to determine its characteristics is the Common Flash Memory Interface (CFI) Specification. The HY29LV320 is fully compliant with this specification.
BLOCK DIAGRAM
DQ[15:0]
A[20:0]
STATE CONTROL COMMAND REGISTER
ERASE VOLTAGE GENERATOR AND SECTOR SWITCHES CFI DATA MEMORY PROGRAM VOLTAGE GENERATOR Y-DECODER I/O CONTROL
I/O BUFFERS
WE# CE# OE# RESET# RY/BY#
CFI CONTROL
DATA LATCH
ADDRESS LATCH
WP#/ACC
Y-GATING 32 Mb FLASH MEMORY ARRAY (67 Sectors)
TIMER
A[20:0]
X-DECODER
VCC DETECTOR
128-word FLASH Security Sector
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HY29LV320
SIGNAL DESCRIPTIONS
Name A[20:0] DQ[15:0] C E# Type Inputs Description Address, active High. These 21 inputs select one of 2,097,152 (2M) words within the array for read or write operations. Inputs/Outputs Data Bus, active High. These pins provide a 16-bit data path for read and Tri-state write operations. Chip Enable, active Low. This input must be asserted to read data from or Input wri te data to the HY29LV320. When Hi gh, the data bus i s tri -stated and the device is placed in the Standby mode. Output Enable, active Low . This input must be asserted for read operations Input and negated for write operations. When High, data outputs from the device are disabled and the data bus pins are placed in the high impedance state. W r ite E n a b le , a c tiv e L o w. C o ntro ls wri ti ng o f c o mma nd s o r c o mma nd Input sequences for various device operations. A write operation takes place when WE# is asserted while CE# is also Low and OE# is High. Hardw are Reset, active Low. Provides a hardware method of resetting the HY29LV320 to the read array state. When the device is reset, it immediately Input terminates any operation in progress. The data bus is tri-stated and all read/write commands are ignored while the input is asserted. While RESET# is asserted the device will be in the Standby mode. R e a d y /B u s y S ta tu s . Ind i c a te s whe the r a wri te o r e ra s e c o mma nd i s i n Output progress or has been completed. Valid after the rising edge of the final WE# Open Drain p ulse o f a co mma nd se q ue nce . Re ma i ns L o w whi le the d e vi ce i s a cti ve ly programming data or erasing, and goes High when it is ready to read array data. Write Protect, active Low/Accelerate (VHH). Placing this pin at VIL disables program and erase operations in the top or bottom 3 2 K wo r d s o f the a r r a y. The a ffe c te d s e c to r s a r e s e c to r s S 0 - S 3 fo r the HY29LV320B and sectors S63 - S66 for the HY29LV320T. If the pin is placed at VIH, the protection state of those two sectors reverts to whether they were last set to be protected or unprotected using the Sector Group Protection and Unprotection capability of the HY29LV320. If V HH i s a p p li e d to thi s i np ut, the d e vi c e e nte rs the Unlo c k B yp a s s mo d e , Input temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. (The system would then use the two -cycle p ro g ra m co mma nd se q ue nce a s re q ui re d b y the Unlo ck B yp a s s mo d e .) Re mo vi ng V HH fro m the p i n re turns the d e vi c e to no rma l operation. This pin must not be at VHH for operations other than accelerated programming, or device damage may result. Leaving the pin floating or unconnected may result in inconsistent device operation. High Input. Connect to VIH or to VCC to provide compatibility with similar x8/x16 Input devices. 3-volt (nominal) pow er supply. --Pow er and signal ground.
OE#
WE#
RESET#
RY/BY#
WP#/ACC
VIH VCC V SS
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PIN CONFIGURATIONS
63- B al F B G A - To p V i , B als F aci D o w n l ew l ng
A8 NC A7 NC B8 NC B7 NC C7 A [13] C6 A [9] C5 W E# C4 D7 A [12] D6 A [8] D5 R E S E T# D4 E7 A [14] E6 A [10] E5 NC E4 F7 A [15] F6 A [11] F5 A [19] F4 A [20] F3 A [5] F2 A [1] G7 A [16] G6 H7 V 10 H6 J7 D Q [15] J6 K7 V55 K6
L8
M8 NC M7 NC
NC
L7
NC
D Q [7] D Q [14] D Q [13] D Q [6] G5 H5 J5 V++ J4 K5 D Q [4] K4
D Q [5] D Q [12] G4 H4
R Y /B Y # W P # /A C C A [18] C3 A [7] A2 NC A1 NC B1 NC C2 A [3] D3 A [17] D2 A [4] E3 A [6] E2 A [2]
D Q [2] D Q [10] D Q [11] D Q [3] G3 H3 J3 K3
D Q [0] D Q [8] D Q [9] D Q [1] G2 A [0] H2 C E# J2 O E# K2 V55 L2 NC L1 NC M2 NC M1 NC
A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[19] A[20] WE# RESET# NC WP#/ACC RY/BY# A[18] A[17] A[7] A[6] A[5] A[4] A[3] A[2] A[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TSOP48
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A[16] V IH V SS DQ[15] DQ[7] DQ[14] DQ[6] DQ[13] DQ[5] DQ[12] DQ[4] V CC DQ[11] DQ[3] DQ[10] DQ[2] DQ[9] DQ[1] DQ[8] DQ[0] OE# V SS CE# A[0]
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HY29LV320
CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (VIH) causes assertion of the signal. A `#' symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in the Low state (VIL). See DC specifications for VIH and VIL values. MEMORY ARRAY ORGANIZATION The 32 Mbit Flash memory array is organized into 67 blocks called sectors (S0, S1, . . . , S66). A sector or several contiguous sectors are defined as a sector group. A sector is the smallest unit that can be erased and a sector group is the smallest unit that can be protected to prevent accidental or unauthorized erasure. In the HY29LV320, four of the sectors, which comprise the boot block, are sized as follows: one of eight Kwords, two of four Kwords and one of sixteen Kwords. The remaining 63 sectors are sized at 32 Kwords. The boot block can be located at the bottom of the address range (HY29LV320B) or at the top of the address range (HY29LV320T). Tables 1 and 2 define the sector addresses and corresponding array address ranges for the top and bottom boot block versions of the HY29LV320. See Tables 6 and 7 for sector group definitions. Secured Sector Flash Memory Region The Secured Sector (Sec2) feature provides a 128 word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). An associated `Sec2 Indicator' bit, which is permanently set at the factory and cannot be changed, indicates whether or not the Sec2 is locked when shipped from the factory. The device is offered with the Sec2 either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Sec2 Indicator bit permanently set to a `1'. The customer-lockable version is shipped with the Sec2 unprotected, allowing customers to utilize the sector in any manner they choose, and has the Sec2 Indicator bit permanently set to a `0'. Thus, the Sec2 Indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. The bit prevents cloning of a factory locked part and thus ensures the security of the ESN once the product is shipped to the field. The system accesses the Sec2 through a command sequence (see "Enter/Exit Secured Sector Command Sequence"). After the system has written the Enter Secured Sector command sequence, it may read the Sec2 by using the addresses specified in Table 3. This mode of operation continues until the system issues the Exit Secured Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to addressing the Flash array.
Note: While in the Sec2 Read mode, only the reading of the `Replaced Sector' (Table 3) is affected. Accesses within the specified sector, but outside the address range specified in the table, may produce indeterminate results. Reading of all other sectors in the device continues normally while in this mode.
Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0]. The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1).
Sec2 Programmed and Protected At the Factory
In a factory-locked device, the Sec2 is protected when the device is shipped from the factory and cannot be modified in any way. The device is available preprogrammed with one of the following:
n A random, secure ESN only n Customer code n Both a random, secure ESN and customer
code In devices that have an ESN, it will be located at the bottom of the sector: starting at word address 0x000000 and ending at 0x000007 for a Bottom Boot device, and starting at word address 0x1FE000 and ending at 0x1FE007 for a Top Boot device. See Table 3.
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Table 1. HY29LV320T (Top Boot Block) Memory Array Organization
SectSiz e or (KWord) A[20] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 28 S 29 S 30 S 31 S 32 S 62 S 63 S 64 S 65 S 66 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 4 4 8 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address 1 A[19] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A[18] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A[17] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A[16] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A[15] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A[14] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A[13] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A[12] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0x000000 - 0x007FFF 0x008000 - 0x00FFFF 0x010000 - 0x017FFF 0x018000 - 0x01FFFF 0x020000 - 0x027FFF 0x028000 - 0x02FFFF 0x030000 - 0x037FFF 0x038000 - 0x03FFFF 0x040000 - 0x047FFF 0x048000 - 0x04FFFF 0x050000 - 0x057FFF 0x058000 - 0x05FFFF 0x060000 - 0x067FFF 0x068000 - 0x06FFFF 0x070000 - 0x077FFF 0x078000 - 0x07FFFF 0x080000 - 0x087FFF 0x088000 - 0x08FFFF 0x090000 - 0x097FFF 0x098000 - 0x09FFFF 0x0A0000 - 0x0A7FFF 0x0A8000 - 0x0AFFFF 0x0B0000 - 0x0B7FFF 0x0B8000 - 0x0BFFFF 0x0C0000 - 0x0C7FFF 0x0C8000 - 0x0CFFFF 0x0D0000 - 0x0D7FFF 0x0D8000 - 0x0DFFFF 0x0E0000 - 0x0E7FFF 0x0E8000 - 0x0EFFFF 0x0F0000 - 0x0F7FFF 0x0F8000 - 0x0FFFFF Same as S0 - S30 except MSD = 1 0x1F8000 - 0x1FBFFF 0x1FC000 - 0x1FCFFF 0x1FD000 - 0x1FDFFF 0x1FE000 - 0x1FFFFF Address Range 2, 3
Same as S0 - S30 except A[20] = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 X 0 0 1 X 0 1 X
Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range is A[20:0].
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HY29LV320
Table 2. HY29LV320B (Bottom Boot Block) Memory Array Organization
SectSiz e or (KWord) A[20] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 28 S 29 S 30 S 31 S 32 S 33 S 34 S 35 S 36 S 66 8 4 4 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Sector Address 1 A[19] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 A[18] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 A[17] 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 A[16] 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 A[15] 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A[14] 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A[13] 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A[12] X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0x000000 - 0x001FFF 0x002000 - 0x002FFF 0x003000 - 0x003FFF 0x004000 - 0x007FFF 0x008000 - 0x00FFFF 0x010000 - 0x017FFF 0x018000 - 0x01FFFF 0x020000 - 0x027FFF 0x028000 - 0x02FFFF 0x030000 - 0x037FFF 0x038000 - 0x03FFFF 0x040000 - 0x047FFF 0x048000 - 0x04FFFF 0x050000 - 0x057FFF 0x058000 - 0x05FFFF 0x060000 - 0x067FFF 0x068000 - 0x06FFFF 0x070000 - 0x077FFF 0x078000 - 0x07FFFF 0x080000 - 0x087FFF 0x088000 - 0x08FFFF 0x090000 - 0x097FFF 0x098000 - 0x09FFFF 0x0A0000 - 0x0A7FFF 0x0A8000 - 0x0AFFFF 0x0B0000 - 0x0B7FFF 0x0B8000 - 0x0BFFFF 0x0C0000 - 0x0C7FFF 0x0C8000 - 0x0CFFFF 0x0D0000 - 0x0D7FFF 0x0D8000 - 0x0DFFFF 0x0E0000 - 0x0E7FFF 0x0E8000 - 0x0EFFFF 0x0F0000 - 0x0F7FFF 0x0F8000 - 0x0FFFFF 0x100000 - 0x107FFF Address Range 2, 3
Same as S4 - S34 except A[20] = 1
Same as S4 - S34 except MSD = 1
Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range is A[20:0].
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Table 3. HY29LV320 Secure Sector Addressing
Device HY29LV320T HY29LV320B Sector Siz e (Words) 128 128 Replaced Sector 1 S66 (Table 1) S0 (Table 2) Address Range 2 0x1FE000 - 0x1FE07F 0x000000 - 0x00007F Electronic Serial Number Address Range 2 0x1FE000 - 0x1FE007 0x000000 - 0x000007
Notes: 1. Accesses within the specified sector, but outside the specified address range, may produce indeterminate results. 2. `0xN. . . N' indicates an address in hexadecimal notation. The address range is A[20:0].
Sec2 NOT Programmed or Protected at the Factory
If the security feature is not required, the Sec2 can be treated as an additional Flash memory space of 128 words. The Sec2 can be read, programmed, and erased as often as required. The Sec2 area can be protected using the following procedure:
tection of the Secure Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secure Sector.
n Once the Secure Sector is locked and verified,
the system must write the Exit Secure Sector command sequence to return to reading and writing the remainder of the array. Sec2 protection must be used with caution since, once protected, there is no procedure available for unprotecting the Sec2 area and none of the bits in the Sec2 memory space can be modified in any way. the memory content occurs during the power transition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register contents are altered. This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host reads from an address within an erase-suspended (or erasing) sector, or while the device is performing a program operation, the device outputs status data instead of array data. After completing an Automatic Program or Erase algorithm within a sector, that sector automatically returns to the read array data mode. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception noted above. The host must issue a hardware reset or the software reset command to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the read array data mode while it is in the Electronic ID mode.
n Write the three-cycle Enter Secure Sector Region command sequence.
n Follow the in-system sector protect algorithm
as shown in Figure 3, except that RESET# may be at either VIH or VID. This allows in-system proBUS OPERATIONS Device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state machine whose outputs control the operation of the device. Table 4 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 5. Data is read from the HY29LV320 by using standard microprocessor read cycles while placing the word address on the device's address inputs. The host system must drive the CE# and OE# pins LOW and drive WE# high for a valid read operation to take place. See Figure 1. The HY29LV320 is automatically set for reading array data after device power-up and after a hardware reset to ensure that no spurious alteration of
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HY29LV320
Table 4. HY29LV320 Normal Bus Operations 1
Operation Read Write Output Disable CE# Normal Standby CE# Deep Standby Hardware Reset (Normal Standby) Hardware Reset (Deep Standby) C E# L L L H VCC 0.3V X X OE# WE# L H H X X X X H L H X X X X R E S E T# H H H H VCC 0.3V L VSS 0.3V WP#/ACC L/H Notes 2, 3 L/H L/H L/H L/H L/H A[20: 0] AIN AIN X X X X X DQ[15: 0] DOUT DIN High-Z High-Z High-Z High-Z High-Z
Notes: 1. L = VIL, H = VIH, X = Don't Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels. 2. If WP#/ACC = VIL, the boot sectors are protected. If WP#/ACC = VIH, the protection state of the boot sectors depends on whether they were last protected or unprotected using the method described in "Sector Group Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 3. See Table 5 for Accelerated Program function with WP#/ACC = VHH.
Table 5. HY29LV320 Bus Operations Requiring High Voltage 1, 2
Operation Accelerated Program Sector Group Protect Sector Unprotect Temporary Sector Unprotect 6 Manufacturer Code D evi ce HY29LV320B C ode HY29LV320T Sector Unprotected Protect Protected State 4 Factory Secure L o cke d Sector Indicator Not Factory Bi t L o cke d CE# OE# WE# RESET# L L L -L L L H H H -L L L L L L -H H H H VID VID VID H H H WP#/ ACC VHH 5 H H Note 4 L/H L/H L/H A[20:12] 3 AIN SGA X -X X SA A[9] AIN X X -VID VID VID A[6] AIN L H -L L L A[1] AIN H H -L L H A[0] DQ[15: 0] 7 AIN L L -L H L 0xXX01 0xXX80 L L H H L/H X VID L H H 0xXX00 CMDIN CMDIN DIN -0x00AD 0x227D 0x227E 0xXX00
Notes: 1. L = VIL, H = VIH, X = Don't Care (L or H), VID = 12V nominal. See DC Characteristics for voltage specifications. 2. Address bits not specified are Don't Care. 3. SA = Sector Address, SGA = Sector Group Address. See Tables 1, 2, 6, and 7. AIN = address input. 4. If WP#/ACC = VIL, the boot sectors remain protected. 5. Protected sectors are temporarily unprotected when VHH is applied to the WP#/ACC pin. 6. Normal read, write and output disable operations are used in this mode. See Table 4. 7. DIN = input data, CMDIN = Command input.
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WE# ADR CE# OE# DATA
OE# ADR CE# tA H WE# tDS DATA
OUT
IN
t ACC t CE t OE
t AS
tDH
Figure 2. Write Operation
Note: WP# sector protection cannot be used while WP#/ ACC = VHH. Thus, all sectors are unprotected and can be erased and programmed while in Accelerated Programming mode. Note: The Accelerate function does not affect the time required for Erase operations.
Figure 1. Read Operation Write Operation Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29LV320. Writes to the device are performed by placing the word address on the device's address inputs while the data to be written is input on DQ[15:0]. The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. See Figure 2. .The "Device Commands" section of this specification provides details on the specific device commands implemented in the HY29LV320. Accelerated Program Operation This device offers accelerated program operations through the "Accelerate" function provided by the WP#/ACC pin. This function is intended primarily for faster programming throughput at the factory. If VHH is applied to the WP#/ACC input, the device enters the Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would then use the two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the pin returns the device to normal operation.
r1.3/May 02
See the description of the WP#/ACC pin in the Pin Descriptions table for additional information on this function. Write Protect Function The Write Protect function provides a hardware method of protecting the boot sectors without using VID. This function is a second function provided by the WP#/ACC pin. Placing this pin at VIL disables program and erase operations in the bottom or top 32K words of the array (the boot sectors). The affected sectors are as follows (see Tables 1 and 2): n HY29LV320B: S0 - S3 n HY29LV320T: S63 - S66 If the pin is placed at VIH, the protection state of those sectors reverts to whether they were last set to be protected or unprotected using the method described in the Sector Group Protection and Unprotection sections.
Note: Sectors protected by WP#/ACC = VIL remain protected during Temporary Sector Unprotect and cannot be erased or programmed. Also see note under Accelerate Program Operation above.
Standby Operation When the system is not reading or writing to the device, it can place the device in the Standby
11
HY29LV320
mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can invoked using two methods. The device enters the CE# Controlled Deep Standby mode when the CE# and RESET# pins are both held at VCC 0.3V. Note that this is a more restricted voltage range than VIH . If both CE# and RESET# are held at VIH , but not within VCC 0.3V, the device will be in the Normal Standby mode, but the standby current will be greater.
Note: If the device is deselected during erasure or programming, it continues to draw active current until the operation is completed.
bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation section. If RESET# is asserted during a program or erase operation (RY/BY# pin is Low), the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which requires a time of tREADY (during Automatic Algorithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation tRB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is High), the reset operation is completed within a time of tRP. In this case, the host can perform a read or write operation tRH after the RESET# pin returns High. The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory. Sector Group Protect Operation The hardware sector group protection feature disables both program and erase operations in any combination of sector groups. A sector group consists of a single sector or a group of adjacent sectors, as specified in Tables 6 and 7. This function can be implemented either in-system or by using programming equipment. It requires a high voltage (VID) on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector protection. The flow chart in Figure 3 illustrates the algorithm. The HY29LV320 is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Electronic ID Mode section for details. Sector Unprotect Operation The hardware sector unprotection feature re-enables both program and erase operations in prer1.3/May 02
The device enters the RESET# Controlled Deep Standby mode when the RESET# pin is held at VSS 0.3V. If RESET# is held at VIL but not within VSS 0.3V, the standby current will be greater. See RESET# section for additional information on the reset operation. The device requires standard access time (tCE) for read access when the device is in any of the standby modes before it is ready to read data. Sleep Mode The sleep mode automatically minimizes device power consumption. This mode is automatically entered when addresses remain stable for tACC + 30 ns (typical) and is independent of the state of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. The device does not enter sleep mode if an automatic program or automatic erase algorithm is in progress. Output Disable Operation When the OE# input is at VIH , output data from the device is disabled and the data bus pins are placed in the high impedance state. Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for the minimum specified period, the device immediately terminates any operation in progress, tri-states the data
12
HY29LV320
Table 6. Sector Groups - Top Boot Version
Group SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 Sectors Group Address Block Siz e (Table 1) A[20: 12] (KWords) S0 0 0 0 0 0 0XXX 32 0 0 0 0 0 1X X X S1 - S3 0 0 0 0 1 0 X X X 96 0 0 0 0 1 1X X X S4 - S7 0 0 0 1 X X X X X 128 S8 -S11 0 0 1 0 X X X X X 128 S 12 - S 15 0 0 1 1 X X X X X 128 S 16 - S 19 0 1 0 0 X X X X X 128 S 20 - S 23 0 1 0 1 X X X X X 128 S 24 - S 27 0 1 1 0 X X X X X 128 S 28 - S 31 0 1 1 1 X X X X X 128 S 32 - S 35 1 0 0 0 X X X X X 128 S 36 - S 39 1 0 0 1 X X X X X 128 S 40 - S 43 1 0 1 0 X X X X X 128 S 44 - S 47 1 0 1 1 X X X X X 128 S 48 - S 51 1 1 0 0 X X X X X 128 S 52 - S 55 1 1 0 1 X X X X X 128 S 56 - S 59 1 1 1 0 X X X X X 128 1 1 1 10 0XXX S 60 - S 62 1 1 1 1 0 1 X X X 96 1 1 1 1 10XXX S 63 1 1 1 1 1 10XX 16 S 64 111111100 4 S 65 11111110 1 4 S 66 1 1 1 1 1 1 1 1X 8
Table 7. Sector Groups - Bottom Boot Version
Group SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 Sectors (Table 2) S0 S1 S2 S3 S4 - S6 S 7 - S 10 S11 - S14 S 15 - S 18 S 19 - S 22 S 23 - S 26 S 27 - S 30 S 31 - S 34 S 35 - S 38 S 39 - S 42 S 43 - S 46 S 47 - S 50 S 51 - S 54 S 55 - S 58 S 59 - S 62 S 63 - S 65 S 66 Group Address Block Siz e A[20: 12] (KWords) 0 0 0 0 000 0X 8 0000000 10 4 0000000 11 4 0 0 0 0 0 0 1X X 16 0 0 0 0 0 1X X X 0 0 0 0 10XXX 96 0 0 0 0 1 1X X X 0 0 0 1XXX X X 128 0 0 10XXXXX 128 0 0 1 1XXX X X 128 0 10 0XXXXX 128 0 1 0 1XXX X X 128 0 1 10XXXXX 128 0 1 1 1XXX X X 128 10 0 0XXXXX 128 1 0 0 1XXX X X 128 10 10XXXXX 128 1 0 1 1XXX X X 128 1 10 0XXXXX 128 1 1 0 1XXX X X 128 1 1 10XXXXX 128 1 1 1 1 0 0XXX 1 1 1 1 0 1X X X 96 1 1 1 1 10XXX 1 1 1 1 1 1X X X 32
viously protected sector groups. This function can be implemented either in-system or by using programming equipment. Note that to unprotect any sector, all unprotected sector groups must first be protected prior to the first sector unprotect write cycle. Also, the unprotect procedure will cause all sectors to become unprotected, thus, sector groups that require protection must be protected again after the unprotect procedure is run. This procedure requires VID on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector unprotection. The flow chart in Figure 4 illustrates the algorithm. Temporary Sector Unprotect Operation This feature allows temporary unprotection of previously protected sector groups to allow changing the data in-system. Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID. While in this mode, formerly protected secr1.3/May 02
tors can be programmed or erased by invoking the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sector groups are protected again. Figure 5 illustrates the algorithm.
NOTE: If WP#/ACC = VIL, the boot sectors remain protected.
Electronic ID Operation (High Voltage Method) The Electronic ID mode provides manufacturer and device identification, sector protection verification and Sec2 region protection status through identifier codes output on DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], with additional requirements for obtain13
HY29LV320
START Wait 150 us R E S E T # = V ID W P # / A C C = V IH R E S E T # = V IH Verify Sector Group Protect: Write 0x40 to Address Write Reset Command Read from Address First Write Cycle: Write 0x60 to device Data = 0x01? TRYCNT = 1 YES Set Address: A[20:12] = Address of Sector Group to be Protected A[6] = 0, A[1] = 1, A[0] = 0 NO Increment TRYCNT DEVICE FAILURE Protect Another Sector Group? NO NO TRYCNT = 25? YES SECTOR GROUP PROTECT COMPLETE
Wait 1 us
Sector Group Protect: Write 0x60 to Address
YES
Figure 3. Sector Group Protect Algorithm
START Note: All sector groups must be protected prior to sector unprotection TRYCNT = 1 SNUM = 0 R E S E T # = V ID W P # / A C C = V IH
Set Address: A[20:12] = Address of Sector Group SNUM A[6] = 1, A[1] = 1, A[0] = 0
R E S E T # = V IH
Verify Unprotect: Write 0x40 to Address
Write Reset Command
Read from Address
SECTOR UNPROTECT COMPLETE
Wait 1 us Data = 0x00? First Write Cycle: Write 0x60 to device YES Set Address: A[6] = 1, A[1] = 1, A[0] = 0 SNUM = 20? Sector Unprotect: Write 0x60 to Address NO Wait 15 ms SNUM = SNUM + 1 NO Increment TRYCNT YES DEVICE FAILURE NO TRYCNT = 1000? YES
Figure 4. Sector Unprotect Algorithm
14
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HY29LV320
ing specific data items listed in Table 5. The Electronic ID data can also be obtained by the host through specific commands issued via the command register, as described later in the `Device Commands' section of this data sheet. While in the high-voltage Electronic ID mode, the system may read at specific addresses to obtain certain device identification and status information:
START
R E S E T # = V ID (All protected sectors become unprotected)
Perform Program or Erase Operations
n A read cycle at address 0xXXX00 retrieves the
manufacturer code.
n A read cycle at address 0xXXX01 returns the
device code.
R E S E T # = V IH (All previously protected sectors return to protected state)
n A read cycle containing a sector address (SA)
in A[20:12] and the address 0x04 in A[7:0] returns 0x01 if that sector is protected, or 0x00 if it is unprotected.
TEMPORARY SECTOR UNPROTECT COMPLETE
n A read cycle at address 0xXXX03 returns 0x80
if the Sec2 region is protected and locked at the factory and 0x00 if it is not. DEVICE COMMANDS Device operations are initiated by writing designated address and data command sequences into the device. Commands are routed to the command register for execution. This register is automatically selected as the destination for all write operations and does not need to be explicitly addressed. Addresses are latched on the falling edge of WE# or CE#, whichever happens later. Data is latched on the rising edge of WE# or CE#, whichever happens first. A command sequence is composed of one, two or three of the following sub-segments: an unlock cycle, a command cycle and a data cycle. Table 8 summarizes the composition of the valid command sequences implemented in the HY29LV320, and these sequences are fully described in Table 9 and in the sections that follow. Writing incorrect address and data values or writing them in the improper sequence resets the device to the Read mode. Reading Data The device automatically enters the read array mode after device power-up, after the RESET# input is asserted and upon the completion of certain commands. Commands are not required to
r1.3/May 02
Figure 5. Temporary Sector Unprotect Algorithm
Table 8. Composition of Command Sequences
Number of Bus Cycles Unlock Command Data Read 0 0 Note 1 Reset 0 1 0 2 1 0 Enter Sec2 Region 2 1 1 Exit Sec2 Region Program 2 1 1 Unlock Bypass 2 1 0 Unlock Bypass 0 1 1 Reset Unlock Bypass 0 1 1 Program Chip Erase 4 1 1 Sector Erase 4 1 1 (Note 2) Erase Suspend 0 1 0 Erase Resume 0 1 0 Electronic ID 2 1 Note 3 CFI Query 0 1 Note 4 Command S eq u en ce
Notes: 1. Any number of Flash array read cycles are permitted. 2. Additional data cycles may follow. See text. 3. Any number of Electronic ID read cycles are permitted. 4. Any number of CFI data read cycles are permitted.
15
HY29LV320
retrieve data in this mode. See Read Operation section for additional information. After the device accepts an Erase Suspend command, the HY29LV320 enters the erase-suspendread mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. Reset Command Writing the Reset command resets the sectors to the Read or Erase-Suspend mode. Address bits are don't cares for this command. As described above, a Reset command is not normally required to begin reading array data. However, a Reset command must be issued in order to read array data in the following cases: tion). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores the Reset command until the operation is complete.
n In a Program command sequence, the Reset
command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command sequence is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores the Reset command until the operation is complete.
n The Reset command may be written between
the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Reset command must be written to return to the array Read mode.
Note: The Reset command does not return the device from Sec2 Region access to normal array access. See descriptions of Enter/Exit Sec2 Region commands for additional information.
n If the device is in the Electronic ID mode, a
Reset command must be written to return to the Read array mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Reset command returns the device to the Erase Suspend mode.
Note: When in the Electronic ID bus operation mode, the device returns to the Read array mode when VID is removed from the A[9] pin. The Reset command is not required in this case.
Enter/Exit Sec2 Region Command Sequences The system can access the Sec2 region of the device by issuing the Enter Sec2 Region Command sequence. The device continues to access the Sec2 region until the system issues the Exit Sec2 Region Command sequence, which returns the device to normal operation. Note that a hardware reset will reset the device to the Read Array mode. Program Command Sequence The system programs the device a word at a time by issuing the appropriate four-cycle Program Command sequence as shown in Table 9. The sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data. This initiates the Automatic Program algorithm that automatically provides internally generated program pulses and verifies the programmed cell margin. The host is not required to provide further controls or timings during this operation. When the Automatic Program algorithm is complete, the device returns to the reading array data mode. Several methods are provided to allow the host to determine the
r1.3/May 02
n If the device is in the CFI Query mode, a Reset
command must be written to return to the array Read mode.
n If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, a Reset command must be invoked to return the sectors to the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend when the Program command was issued). The Reset command may also be used to abort certain command sequences:
n In a Sector Erase or Chip Erase command sequence, the Reset command may be written at any time before erasing actually begins, including, for the Sector Erase command, between the cycles that specify the sectors to be erased (see Sector Erase command descrip16
Electronic ID 11
r1.3/May 02
Table 9. HY29LV320 Command Sequences
Bus Cycles 1, 2, 3, 4 Command Sequence
Read Reset Enter Sec 2 Region Exit Sec Region Normal Program Unlock Bypass Unlock Bypass Reset Unlock Bypass Program 5 Chip Erase Sector Erase 9 Erase Suspend 7 Erase Resume 8 Manufacturer Code Device Code Sector Protect Verify
6 2 7
First Write Cycles Add Data
0 1 3 4 4 3 2 2 6 6 1 1 3 3 3 3 RA XXX 555 555 555 555 XXX XXX 555 555 XXX XXX 555 555 555 555 X X X 55 RD F0 AA AA AA AA 90 A0 AA AA B0 30 AA AA AA AA
S eco n d Add Data
Third Add Data
Fourth Add Data
Fifth Add Data
Sixth Add Data
2A A 2A A 2A A 2A A XXX PA 2A A 2A A
55 55 55 55 00 PD 55 55
555 555 555 555
88 90 A0
XXX
PA
00 PD
20
555 555
80 80
555 555
AA AA
2A A 2A A
55 55
555 SA
10 30
2A A 2A A 2A A 2A A
55 55 55
555 555 555 555
90 90 90
X X X 00 00A D XXX01 Bottom Boot = 227D, Top Boot = 227E (SA)X02 X X X 03 XX00 = Unprotected Sector XX01 = Protected Sector XX00 = NOT protected and locked at factory XX80 = Protected and locked at factory
Sec2 Region Indicator Bit
55
90
Common Flash Interface (CFI) Query 10
1
98
RA/RD = Memory address/data for the read operation SA = A[20:12], sector address of the sector to be erased or verified (see Tables 1 and 2).
Legend: X = Don't Care PA/PD = Memory address/data for the program operation
Notes: 1. All values are in hexadecimal. 2. All bus cycles are write operations except all cycles of the Read command and the fourth cycle of Electronic ID command. 3. Data bits DQ[15:8] are don't cares except for `PD' in program cycles. 4. Address is A[10:0]. Other (upper) address bits are don't cares except when `SA' or `PA' is required. 5. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 6. The Unlock Bypass Reset command is valid only while the device is in the Unlock Bypass mode. 7. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode. 8. The Erase Resume command is valid only during the Erase Suspend mode. 9. Multiple sectors may be specified for erasure. See command description. 10.See CFI section of specification for additional information. 11. See Electronic ID section of specification for additional information.
HY29LV320
17
HY29LV320
status of the programming operation, as described in the Write Operation Status section. Commands written to the device during execution of the Automatic Program algorithm are ignored. Note that a hardware reset immediately terminates the programming operation (see Reset Operation Timings). To ensure data integrity, the user should reinitiate the aborted Program Command sequence after the reset operation is complete. Programming is allowed in any sequence. Only erase operations can convert a stored "0" to a "1". Thus, a bit cannot be programmed from a "0" back to a "1". Attempting to do so will cause the HY29LV320 to halt the operation and set DQ[5] to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Figure 6 illustrates the programming operation. Unlock Bypass Command Sequence Unlock bypass provides a faster method than the normal Program Command for the host system to program the array. As shown in Table 9, the Unlock Bypass Command sequence consists of two unlock write cycles followed by a third write cycle containing the unlock bypass command, 0x20. The device then enters Unlock Bypass mode. In this mode, a two-cycle Unlock Bypass Program Command sequence is used instead of the standard four-cycle sequence to invoke a programming operation. The first cycle in this sequence contains the unlock bypass program command, 0xA0, and the second cycle specifies the program address and data, thus eliminating the initial two unlock cycles required in the standard Program Command sequence. Additional data is programmed in the same manner. The unlock bypass mode does not affect normal read operations. During the unlock bypass mode, only the Unlock Bypass Program and the Unlock Bypass Reset commands are valid. To exit the Unlock Bypass mode, the host must issue the two-cycle Unlock Bypass Reset command sequence shown in Table 9. Figure 6 illustrates the procedures for the normal and unlock bypass program operations. The device automatically enters the unlock bypass mode when it is placed in Accelerate mode via the ACC pin.
START Check Programming Status (See Write Operation Status Section) Enable Fast Programming? DQ[5] Error Exit
NO
Programming Verified
YES Issue UNLOCK BYPASS Command
NO
Last Word/Byte Done?
YES Setup Next Address/Data for Program Operation
NO
Unlock Bypass Mode?
NO
Unlock Bypass Mode?
YES Issue UNLOCK BYPASS RESET Command
Issue NORMAL PROGRAM Command
YES Issue UNLOCK BYPASS PROGRAM Command PROGRAMMING COMPLETE GO TO ERROR RECOVERY PROCEDURE
Figure 6. Normal and Unlock Bypass Programming Procedures
18
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HY29LV320
Chip Erase Command Sequence The Chip Erase Command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the Chip Erase Command. This sequence invokes the Automatic Chip Erase algorithm which automatically preprograms (if necessary) and verifies the entire memory for an all zero data pattern before electrical erase. The host system is not required to provide any controls or timings during these operations. If all sectors in the device are protected, the device returns to reading array data after approximately 100 s. If at least one sector is unprotected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. Reads from the device during operation of the Automatic Chip Erase Algorithm return status data. See Write Operation Status section of this specification. Commands written to the device during execution of the Automatic Chip Erase algorithm are ignored. Note that a hardware reset immediately terminates the chip erase operation (see Hardware Reset Timings). To ensure data integrity, the user should reinitiate the aborted Chip Erase Command sequence after the reset operation is complete. When the Automatic Chip Erase algorithm is complete, the device returns to the reading array data mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 7 illustrates the chip erase procedure.
START
Sector Erase Command Sequence The Sector Erase Command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the Sector Erase Command, which specifies which sector is to be erased. This sequence invokes the Automatic Sector Erase algorithm which automatically preprograms (if necessary) and verifies the specified sector for an all zero data pattern before electrical erase. The host system is not required to provide any controls or timings during these operations. After the sector erase command cycle (sixth cycle) of the command sequence is issued, a sector erase time-out of 50 s (min) begins, measured from the rising edge of the final WE# pulse in the command sequence. During this time, an additional sector address and Sector Erase Command may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sectors designated for erasure may be from one sector to all sectors. The only restriction is that the time between these additional cycles must be less than 50 s, otherwise erasure may begin before the last address and command are accepted. To ensure that all commands are accepted, it is recommended that host processor interrupts be disabled during the time that the additional sector erase commands are being issued and then be re-enabled afterwards. The system can monitor DQ[3] to determine if the 50 s sector erase time-out has expired, as described in the Write Operation Status section. If the time between additional sector erase commands can be assured to be less than the timeout, the system need not monitor the timeout.
Note: Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any additional sector addresses and commands. Once the sector erase operation itself has begun, only the Erase Suspend command is valid. All other commands are ignored.
Issue CHIP ERASE Command Sequence
Check Erase Status (See Write Operation Status Section) Normal Exit
DQ[5] Error Exit
CHIP ERASE COMPLETE
GO TO ERROR RECOVERY
As for the chip erase command, note that a hardware reset immediately terminates the erase operation (see Hardware Reset Timings). To ensure data integrity, the aborted sector erase command sequence should be reissued once the reset operation is complete.
Figure 7. Chip Erase Procedure
r1.3/May 02
19
HY29LV320
If all sectors designated for erasing are protected, the device returns to reading array data after approximately 100 s. If at least one designated sector is unprotected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. Read array operations cannot take place until the Automatic Erase algorithm terminates, or until the erase operation is suspended. Read operations while the algorithm is in progress provide status data. When the Automatic Erase algorithm is complete, the device returns the erased sector(s) to the Read (array data) mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 8 illustrates the sector erase procedure. Erase Suspend/Erase Resume Commands The erase suspend command allows the system to interrupt a sector erase operation to program data into, or to read data from, any sector not designated for erasure. The command causes the erase operation to be suspended in all sectors designated for erasure. This command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the
START Check Erase Status DQ[5] Error Exit (See Write Operation Status Section) Write First Five Cycles of SECTOR ERASE Command Sequence Normal Exit
command sequence, and is ignored if it is issued during chip erase or programming operations. The HY29LV320 requires a maximum of 20 s to suspend the erase operation if the erase suspend command is issued during active sector erasure. However, if the command is written during the sector erase time-out, the time-out is terminated and the erase operation is suspended immediately. Once the erase operation has been suspended, the system can read array data from or program data into any sector that is not designated for erasure (protected sectors cannot be programmed). Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ[7:0]. The host can use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspended read state and the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the erase-suspended state just as in the standard programming operation.
Setup First (or Next) Sector Address for Erase Operation
ERASE COMPLETE
GO TO ERROR RECOVERY
Write Last Cycle (SA/0x30) of SECTOR ERASE Command Sequence NO Sector Erase Time-out (DQ[3]) Expired?
Sectors that require erasure but which were not specified in this erase cycle must be erased later using a new command sequence
Erase An Additional Sector?
YES
YES
NO
Figure 8. Sector Erase Procedure
20
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HY29LV320
The host may also write the Electronic ID Command sequence when the chip is in the Erase Suspend mode. The device allows reading Electronic ID codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the Electronic ID mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Electronic ID Mode section for more information. The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
Note: If an erase operation is started while in the Sec2 region and then suspended to do other operations, the host must return the device to the Sec2 region before issuing the Erase Resume command. Failure to do this may result in the wrong sector being erased.
n A read cycle at address 0xXXX00 retrieves the
manufacturer code.
n A read cycle at address 0xXXX01 in returns
the device code.
n A read cycle containing a sector address (SA)
in A[20:12] and the address 0x02 in A[7:0] returns 0x01 if that sector is protected, or 0x00 if it is unprotected.
n A read cycle at address 0xXXX03 returns 0x80
if the Sec2 region is protected and locked at the factory and returns 0x00 if it is not.
The system must write the Reset command to exit the Electronic ID mode and return the bank to the normal Read mode, or to the Erase-Suspended read mode if the device was in that mode when the Electronic ID command was invoked. In the latter case, an Erase Resume command to that bank will continue the suspended erase operation. Query Command and Common Flash Interface (CFI) Mode The HY29LV320 is capable of operating in the Common Flash Interface (CFI) mode. This mode allows the host system to determine the manufacturer of the device, its operating parameters, its configuration and any special command codes that the device may accept. With this knowledge, the system can optimize its use of the chip by using appropriate timeout values, optimal voltages and commands necessary to use the chip to its full advantage. Two commands are employed in association with CFI mode. The first places the device in CFI mode (Query command) and the second takes it out of CFI mode (Reset command). These are described in Table 10. The single cycle Query command is valid only when the device is in the Read mode, including during Erase Suspend and Standby states and while in Electronic ID command mode, but is ignored otherwise. The command is not valid while the HY29LV320 is in the Electronic ID bus operation mode. Read cycles at appropriate addresses while in the Query mode provide CFI data as described later in this section. Write cycles are ignored, except for the Reset command. The Reset command returns the device from the CFI mode to the array Read mode (even if it was
21
Electronic ID Command The Electronic ID mode provides manufacturer and device identification and sector protection verification through identifier codes output on DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], as described previously in the Device Operations section. The Electronic ID data can also be obtained by the host through specific commands issued via the command register, as shown in Table 9. This method does not require VID. The Electronic ID command sequence may be issued while the device is in the Read mode or in the Erase Suspend Read mode. The command may not be written while the device is actively programming or erasing. The Electronic ID command sequence is initiated by writing two unlock cycles, followed by a third write cycle that contains the Electronic ID command. The device then enters the Electronic ID mode, and the system may read at any address any number of times without initiating another command sequence.
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HY29LV320
in the Electronic ID mode when the Query command was issued), or to the Erase Suspend mode if the device was in that mode prior to entering CFI mode. The Reset command is valid only when the device is in the CFI mode and as otherwise described for the normal Reset command. Table 10. CFI Mode: Identification Data Values
Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) Address 10 11 12 13 14 15 16 17 18 19 1A Data 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000
Tables 10 - 13 specify the data provided by the HY29LV320 during CFI mode. Data at unspecified addresses reads out as 0x00. Note that a value of 0x00 for a data item normally indicates that the function is not supported. All values in these tables are in hexadecimal notation.
22
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HY29LV320
Table 11. CFI Mode: System Interface Data Values
Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N s) Typical timeout for maximum size buffer write (2N s) Typical timeout for individual block erase (2N ms) Typical timeout for full chip erase (2N ms) Maximum timeout for single word/byte write (2N x Typ) Maximum timeout for maximum size buffer write (2N x Typ) Maximum timeout for individual block erase (2N x Typ) Maximum timeout for full chip erase (not supported) Address 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Data 0027 0036 0000 0000 0004 0000 0009 000F 0005 0000 0004 0000
Table 12. CFI Mode: Device Geometry Data Values
Description Device size (2 bytes) Flash device interface code (01 = asynchronous x16) Maximum number of bytes in multi-byte write (not supported) Number of erase block regions Erase block region 1 information
[2E, 2D] = # of blocks in region - 1 [30, 2F] = size in multiples of 256-bytes
N
Address 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C
Data 0016 0001 0000 0000 0000 0004 0000 0000 0040 0000 0001 0000 0020 0000 0000 0000 0080 0000 003E 0000 0000 0001
Erase block region 2 information
Erase block region 3 information
Erase block region 4 information
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23
HY29LV320
Table 13. CFI Mode: Vendor-Specific Extended Query Data Values
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0 = required, 1 = not required) Erase suspend(2 = to read and write) Sector protect (N = # of sectors/group) Temporary sector unprotect (1 = supported) Sector protect/unprotect scheme (4 = Am29LV800A method) Simultaneous R/W operation (xx = number of sectors in Bank 2: 0 = not supported) Burst mode type (0 = not supported) Page mode type (0 = not supported) ACC Supply minimum (11.5V) ACC Supply maximum (12.5V) Top/bottom boot version (BB = Bottom Boot, TB = Top Boot) Address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Data 0050 0052 0049 0031 0030 0000 0002 0001 0001 0004 0000 0000 0000 00B 5 00C 5 0002 (BB) 0003 (TB)
WRITE OPERATION STATUS The HY29LV320 provides a number of facilities to determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. Table 11 summarizes the status indications and further detail is provided in the subsections which follow. RY/BY# - Ready/Busy# RY/BY# is an open-drain output pin that indicates whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up resistor to VCC is required for proper operation. RY/ BY# is valid after the rising edge of the final WE# pulse in the corresponding command sequence. If the output is Low (busy), the device is actively erasing or programming, including programming while in the Erase Suspend mode. If the output is High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the Standby mode. DQ[7] - Data# Polling The Data# ("Data Bar") Polling bit, DQ[7], indicates to the host system whether an Automatic Algo24
rithm is in progress or completed, or whether the device is in Erase Suspend mode. Data# Polling is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence. The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is in progress, the device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 1 s, then the device returns to reading array data. The host must read at an address within any nonprotected sector specified for erasure to obtain valid erase status information on DQ[7]. During an erase operation, Data# Polling produces a "0" on DQ[7]. When the erase operation is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ[7]. If all sectors selected for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 s, then the device returns to reading array data. If at least one selected sector is not protected, the erase operation erases the unprotected sectors,
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HY29LV320
Table 14. Write and Erase Operation Status Summary 1
Mode Operation Programming in progress Normal Programming completed Erase in progress Erase completed 5 Read within erase suspended sector Read within non-erase Erase Suspend suspended sector Programming in progress 6 Programming completed
6
DQ[7] DQ[7]# Data 0 Data 1 Data DQ[7]# Data
DQ[6] Toggle Data
4
DQ[5] 0/1 0/1
2
DQ[3] N/A Data 1
3
DQ[2] N/A Data Toggle Data 4 Toggle Data N/A Data
RY/BY# 0 1 0 1 1 1 0 1
Data
2
Toggle Data 4 No toggle Data Toggle Data
4
Data 0 Data 0/1 2 Data
Data N/A Data N/A Data
Notes: 1. A valid address is required when reading status information (except RY/BY#). For a programming operation, the address used for the read cycle should be the program address. For an erase operation, the address used for the read cycle should be any address within a non-protected sector marked for erasure (any address within a non-protected sector for the chip erase operation). 2. DQ[5] status switches to a `1' when a program or erase operation exceeds the maximum timing limit. 3. A `1' during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. DQ[3] is not applicable to the chip erase operation. 4. Equivalent to `No Toggle' because data is obtained in this state. 5. Data (DQ[7:0]) = 0xFF immediately after erasure. 6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
and ignores the command for the specified sectors that are protected. When the system detects that DQ[7] has changed from the complement to true data (or "0" to "1" for erase), it should do an additional read cycle to read valid data from DQ[7:0]. This is because DQ[7] may change asynchronously with respect to the other data bits while Output Enable (OE#) is asserted low. Figure 9 illustrates the Data# Polling test algorithm. DQ[6] - Toggle Bit I Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence, including during the sector erase time-out. The system may use either OE# or CE# to control the read cycles. Successive read cycles at any address during an Automatic Program algorithm operation (including programming while in Erase Suspend mode) cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within
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a protected sector, DQ[6] toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. While the Automatic Erase algorithm is operating, successive read cycles at any address cause DQ[6] to toggle. DQ[6] stops toggling when the erase operation is complete or when the device is placed in the Erase Suspend mode. The host may use DQ[2] to determine which sectors are erasing or erase-suspended (see below). After an Erase command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for approximately 100 s, then returns to reading array data. If at least one selected sector is not protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. DQ[2] - Toggle Bit II Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ[2] with each OE# or CE# read cycle.
25
HY29LV320
START
Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? YES
limit. This is a failure condition that indicates that the program or erase cycle was not successfully completed. DQ[5] status is valid only while DQ[7] or DQ[6] indicate that the Automatic Algorithm is in progress. The DQ[5] failure condition will also be signaled if the host tries to program a `1' to a location that is previously programmed to `0', since only an erase operation can change a `0' to a `1'. For both of these conditions, the host must issue a Reset command to return the device to the Read mode.
Note: While DQ[5] indicates an error condition, no commands (except Reads) will be accepted by the device. If the device receives a command while DQ[5] is high, the first write cycle of that command will reset the error condition and the remaining write cycles of that command sequence will be ignored
NO
NO
DQ[5] = 1?
YES Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? (Note 2) YES
DQ[3] - Sector Erase Timer After writing a Sector Erase command sequence, the host may read DQ[3] to determine whether or not an erase operation has begun. When the sector erase time-out expires and the sector erase operation commences, DQ[3] switches from a `0' to a `1'. Refer to the "Sector Erase Command" section for additional information. Note that the sector erase timer does not apply to the Chip Erase command. After the initial Sector Erase command sequence is issued, the system should read the status on DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ[3]. If DQ[3] is a `1', the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ[3] is a `0', the device will accept a sector erase data cycle to mark an additional sector for erasure. To ensure that the data cycles have been accepted, the system software should check the status of DQ[3] prior to and following each subsequent sector erase data cycle. If DQ[3] is high on the second status check, the last data cycle might not have been accepted.
NO PROGRAM/ERASE EXCEEDED TIME ERROR PROGRAM/ERASE COMPLETE
Notes: 1. During programming , the program address. During sector erase , an address within any non-protected sector specified for erasure. During chip erase , an address within any non-protected sector. 2. Recheck DQ[7] since it may change asynchronously to DQ[5].
Figure 9. Data# Polling Test Algorithm DQ[2] toggles when the host reads at addresses within sectors that have been specified for erasure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot distinguish which sectors are specified for erasure. Thus, both status bits are required for sector and mode information. Figure 10 illustrates the operation of Toggle Bits I and II. DQ[5] - Exceeded Timing Limits DQ[5] is set to a `1' when the program or erase time has exceeded a specified internal pulse count
26
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HY29LV320
START
DQ[5] = 1? Read DQ[7:0] at Valid Address (Note 1) NO YES Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] Read DQ[7:0]
YES NO (Note 4) DQ[6] Toggled?
NO
DQ[6] Toggled? (Note 2)
NO DQ[2] Toggled?
NO (Note 3) PROGRAM/ERASE COMPLETE
YES PROGRAM/ERASE EXCEEDED TIME ERROR
YES SECTOR BEING READ IS IN ERASE SUSPEND SECTOR BEING READ IS NOT IN ERASE SUSPEND
Notes: 1. During programming, the program address. During sector erase, an address within any sector scheduled for erasure. 2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1. 3. Use this path if testing for Program/Erase status. 4. Use this path to test whether sector is in Erase Suspend mode.
Figure 10. Toggle Bit I and II Test Algorithm HARDWARE DATA PROTECTION The HY29LV320 provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. These methods are described in the sections that follow. Command Sequences Commands that may alter array data require a sequence of cycles as described in Table 9. This provides data protection against inadvertent writes. Low VCC Write Inhibit To protect data during VCC power-up and powerdown, the device does not accept write cycles when VCC is less than VLKO (typically 2.4 volts). The command register and all internal program/erase circuits are disabled, and the device resets to the Read mode. Writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
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Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by asserting any one of the following conditions: OE# = VIL , CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the Read mode on power-up. Sector Protection Additional data protection is provided by the HY29LV320's sector protect feature, described previously, which can be used to protect sensitive areas of the Flash array from accidental or unauthorized attempts to alter the data.
27
HY29LV320
ABSOLUTE MAXIMUM RATINGS 4
Symbol TSTG TBIAS VIN2 IOS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage on Pin with Respect to VSS : VCC 1 A[9], OE#, WP#/ACC, RESET# 2 All Other Pins 1 Output Short Circuit Current 3 Value -65 to +150 -65 to +125 -0.5 to +4.0 -0.5 to +12.5 -0.5 to (VCC + 0.5) 200 Unit C C V V V mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 11. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 12. 2. Minimum DC input voltage on pins A[9], WP#/ACC, OE#, and RESET# is -0.5 V. During voltage transitions, A[9], WP#/ ACC, OE#, and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 11. Maximum DC input voltage on pins A[9], WP#/ACC, OE# and RESET# is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS 1
Symbol TA V CC Parameter Ambient Operating Temperature: Commercial Temperature Devices Industrial Temperature Devices Operating Supply Voltage Value 0 to +70 -40 to +85 Note 2 Unit C C V
Notes: 1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed. 2. See Valid Combinations table, page 43.
20 ns 0.8 V - 0.5 V
20 ns V C C + 2.0 V
20 ns
V C C + 0.5 V - 2.0 V 20 ns 2.0 V 20 ns 20 ns
Figure 11. Maximum Undershoot Waveform
Figure 12. Maximum Overshoot Waveform
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HY29LV320
DC CHARACTERISTICS
Parameter ILI ILIT ILO ICC1 ICC2 ICC3 Description Input Load Current A[9], Input Load Current Output Leakage Current VCC Active Read Current 1 VCC Active Write Current 3, 4 VCC CE# Controlled Deep Standby Current VCC RESET# Controlled Deep Standby Current Automatic Sleep Mode Current 5, Accelerated Program Current 4 Test Setup 2 VIN = VSS to VCC A[9] = 12.5V VOUT = VSS to VCC 5 MHz 1 MHz CE# = VIL, OE# = VIH CE# = VCC 0.3 V, RESET# = VCC 0.3 V, WP#/ACC = VCC 0.3 V or VSS 0.3 V RESET# = VSS 0.3 V, WP#/ACC = VCC 0.3 V or VSS 0.3 V VIH = VCC 0.3 V, VIL = VSS 0.3 V VHH CE# = VIL OE# = VIH V CC CE# = VIL, OE# = VIH, -0.5 0.7 x VCC 11.5 11.5 9 2 20 0.5 Min Typ Max 1.0 35 1.0 16 4 30 5 Unit A A A mA mA mA A
ICC4 ICC5 IACC VIL VIH VID VHH VOL VOH1 VOH2 V LK O
0.5 0.5 5 15
5 5 10 30 0.8 VCC + 0.3 12.5 12.5 0.45
A A mA mA V V V V V V V
Input Low Voltage Input High Voltage Voltage for Electronic ID and VCC = 3.0V 10% Temporary Sector Unprotect Voltage for Program VCC = 3.0V 10% Acceleration VCC = VCC Min, Output Low Voltage IOL = 4.0 mA VCC = VCC Min, IOH = -2.0 mA Output High Voltage VCC = VCC Min, IOH = -100 A 4 Low VCC Lockout Voltage
0.85 x VCC VCC - 0.4 2.3 2.5
V
Notes: 1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V. 2. All maximum current specifications are tested with VCC = VCC Max unless otherwise noted. 3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress. 4. Not 100% tested. 5. Automatic sleep mode is enabled when addresses remain stable for tACC + 50 ns (typical).
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29
HY29LV320
DC CHARACTERISTICS Zero Power Flash
20
15 Supply Current in mA
10
5
0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000
Note: Addresses are switching at 1 MHz.
Figure 13. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6 V
8 Supply Current in mA
2.7 V
6
4
2
0 1
Note: TA = 25 C.
2
3 Frequency in MHz
4
5
6
Figure 14. Typical ICC1 Current vs. Frequency
30
r1.3/May 02
HY29LV320
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUT S Steady OUT PUT S
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown Centerline is High Impedance State (High Z)
Does Not Apply
TEST CONDITIONS Table 15. Test Specifications
+ 3.3V
Test C ondition - 70 - 80 - 90 - 12 100 5 0.0 3.0 1.5 1.5 U nit
2.7 KOhm DEVICE UNDER TEST CL 6.2 KOhm
Output Load Output Load C apaci tance (C L) Input Ri se and Fall Ti mes Input Si gnal Low Level Input Si gnal Hi gh Level Low Ti mi ng Measurement Si gnal Level Hi gh Ti mi ng Measurement Si gnal Level 30
1 TTL Gate pF ns V V V V
All diodes are 1N3064 or equivalent
Figure 15. Test Setup
Note: Timing measurements are made at the reference levels specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurements are made.
3.0 V Input 0.0 V 1.5 V Measurement Level 1.5 V Output
Figure 16. Input Waveforms and Measurement Levels
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31
HY29LV320
AC CHARACTERISTICS Read Operations
Parameter JE D E C tAVAV tAVQV tELQV tEHQZ tGLQV tGHQZ Std tRC tACC tCE tDF tOE tDF tOEH tAXQX tOH Description Read Cycle Time 1 Address to Output Delay Chip Enable to Output Delay Chip Enable to Output High Z 1 Output Enable to Output Delay Output Enable to Output High Z 1 Read Output Enable Toggle and Hold Time 1 Data# Polling Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First 1 CE# = VIL OE# = VIL OE# = VIL CE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Option - 70 - 80 70 70 70 25 30 25 80 80 80 25 30 30 0 10 0 - 90 90 90 90 30 35 30 - 12 120 120 120 30 50 30 Unit ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See Figure 15 and Table 15 for test conditions.
tR C Addresses Addresses Stable tA C C CE# tO E OE# tO E H WE# tC E tD F
tO H Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 17. Read Operation Timings
32
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HY29LV320
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Automatic Algorithms) to Read or Write 1 RESET# Pin Low (NOT During Automatic Algorithms) to Read or Write 1 RESET# Pulse Width RESET# High Time Before Read 1 RESET# Low to Standby Mode RY /BY # Recovery Time Test Setup Max Max Min Min Max Min Speed Option - 70 - 80 - 90 20 500 500 50 20 0 - 12 Unit s ns ns ns s ns
Notes: 1. Not 100% tested. 2. See Figure 15 and Table 15 for test conditions.
RY/BY# CE#, OE#
0V
tR H RESET# tR P t Ready
Reset Timings NOT During Automatic Algorithms
RY/BY# CE#, OE# RESET# tR P
t Ready tRB
Reset Timings During Automatic Algorithms Figure 18. RESET# Timings
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33
HY29LV320
AC CHARACTERISTICS Program and Erase Operations
Parameter JE D E C tAVAV tAVWL tWLAX Std tWC tAS tAH tAST tAHT tCEPH tOEPH tDS tDH tGHWL tCS tCH tWP tWPH Description Write Cycle Time 1 Address Setup Time Address Hold Time Address Setup Time to OE# or CE# Low for Toggle Bit Test Address Hold Time from OE# or CE# High for Toggle Bit Test Chip Enable High Time for Toggle Bit Test Output Enable High Time for Toggle Bit Test Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ
1
Speed Option - 70 - 80 70 45 80 0 45 15 0 20 20 45 45 0 0 0 0 35 35 35 30 11 300 23 70 7 210 0.5 7.5 32 100,000 1,000,000 50 250 0 90 50 45 50 45 50 - 90 90 - 12 120
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s se c se c s s se c se c se c cycles cycles s ns ns ns
tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1
tWHWH1 Word Programming Operation 1, 2, 3 Chip Programming Operation 1, 2, 3, 5
tWHWH1 tWHWH2 tWHWH3
tWHWH1 Accelerated Word Programming Operation 1, 2, 3 tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Erase and Program Cycle Endurance tVCS tVHH tRB tBUSY VCC Setup Time 1 VHH Rise and Fall Time 1 Recovery Time from RY/BY# WE# High to RY/BY# Delay
Min Typ Min Min Min Min
Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 2.7 volts (3.0 volts for - 70 version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 9 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum word program time specified is exceeded. See Write Operation Status section for additional information.
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HY29LV320
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tW C Addresses CE# tG H W L OE# WE# tC S tD S 0xA0 tW P 0x555
tA S PA
tA H PA PA
tC H tW P H tD H tW H W H 1 PD tB U S Y Status D OUT tR B
Data
RY/BY# V CC tV C S
Notes: 1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address. 2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 19. Program Operation Timings
VHH
ACC
V IL or V IH V IL or V IH
tV H H
tV H H
Figure 20. Accelerated Programming Voltage Timings
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35
HY29LV320
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data (last two cycles)
tW C Addresses CE# tG H W L OE# tW P WE# tC S tD S tC H 0x2AA
tA S SA
tA H VA
Address = 0x555 for chip erase
VA
tW P H tD H
Data = 0x10 for chip erase
t W H W H 2 or tW H W H 3 Status D OUT tR B
Data
0x55
0x30 tB U S Y
RY/BY# V CC tV C S
Notes: 1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section), DOUT is the true data at the read address.(0xFF after an erase operation). 2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 21. Sector/Chip Erase Operation Timings
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HY29LV320
AC CHARACTERISTICS
tR C Addresses tC H CE# tC E OE# tO E H WE# tO E tD F tO H
Complement Complement True Valid Data
VA tA C C
VA
VA
DQ[7] DQ[6:0] tB U S Y RY/BY#
Status Data
Status Data
Data
Valid Data
Notes: 1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section). 2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 22. Data# Polling Timings (During Automatic Algorithms)
tA C C tR C Addresses tC H tA S T CE# tO E OE# tO E H WE# tD F tO H
Valid Status Valid Status (second read) Valid Status (stops toggling) Valid Data
VA tA H T tC E tC E P H tO E P H
VA
VA
VA
DQ[6], [2] tB U S Y RY/BY#
(first read)
Notes: 1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section). 2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 23. Toggle Bit Timings (During Automatic Algorithms)
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37
HY29LV320
AC CHARACTERISTICS
Enter Automatic Erase Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
WE#
DQ[6] DQ[2]
Notes: 1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an erase-suspended sector.
Figure 24. DQ[2] and DQ[6] Operation Sector Protect and Unprotect, Temporary Sector Unprotect
Parameter JE D E C Std tVIDR tRSP tVRST tPROT tUNPR Description VID Transition Time for Temporary Sector Unprotect 1 RESET# Setup Time for Temporary Sector Unprotect RESET# Setup Time for Sector Group Protect and Sector Unprotect Sector Group Protect Time Sector Unprotect Time Min Min Min Max Max Speed Option - 70 - 80 - 90 - 12 500 4 1 150 15 Unit ns s s s ms
Notes: 1. Not 100% tested.
V ID
RESET#
0 or 3V 0 or 3V
t VIDR
t VIDR
CE#
WE# tR S P RY/BY#
Figure 25. Temporary Sector Unprotect Timings
38
r1.3/May 02
HY29LV320
AC CHARACTERISTICS
V ID V IH
RESET#
SGA, A[6], A[1], A[0] Data
tV R S T
Don't Care
Valid *
Valid * Verify 0x40 t P R O T or t U N P R
Valid *
Sector Group Protect/ Sector Unprotect 0x60 0x60
Status
CE#
WE#
OE#
Note: For Sector Group Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0.
Figure 26. Sector Group Protect and Sector Unprotect Timings AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations
Parameter JE D E C tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tBUSY Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to CE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High CE# High to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Speed Option - 70 - 80 70 45 45 80 0 45 45 0 0 0 0 35 35 30 90 35 50 45 45 50 50 - 90 90 - 12 120 Unit ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See Programming and Erase Operations table for Erase, Program and Endurance characterisitics.
r1.3/May 02
39
HY29LV320
AC CHARACTERISTICS
PA for Program SA for Sector Erase 0x555 for Chip Erase
0x555 for Program 0x2AA for Erase
Addresses tW C WE# tG H E L OE# tW S CE# tD S Data
0xA0 for Program 0x55 for Erase PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA tA S tA H
tW H tC P tC P H t W H W H 1 or t W H W H 2 or t W H W H 3 tB U S Y Status D OUT
tD H
RY/BY# tR H RESET#
Notes: 1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Operation Status section), DOUT = array data read at VA. 2. 3. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence.
Figure 27. Alternate CE# Controlled Write Operation Timings
40
r1.3/May 02
HY29LV320
Latchup Characteristics
Description Input voltage with respect to VSS on all pins except I/O pins (including WP#/ACC, A[9], OE# and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Minimum - 1.0 - 1.0 - 100 Maximum 12.5 VCC + 1.0 100 Unit V V mA
Notes: 1. Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
TSOP Pin Capacitance
Symbol CIN COUT CIN2 Parameter Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions: TA = 25 C, f = 1.0 MHz.
Data Retention
Parameter Minimum Pattern Data Retention Time Test Conditions 150 C 125 C Minimum 10 20 Unit Years Years
PACKAGE DRAWINGS Physical Dimensions TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)
0.95 1.05 Pin 1 ID
1 48
11.90 12.10
0.50 BSC
24
25
18.30 18.50 19.80 20.20
0.05 0.15
1.20 MAX 0.25MM (0.0098") BSC 0 o 5 0.50 0.70
r1.3/May 02
o
0.08 0.20 0.10 0.21
41
HY29LV320
PACKAGE DRAWINGS Physical Dimensions FBGA63 - 63-Ball Fine-Pitch Ball Grid Array, 7.0 x 11 mm (measurements in millimeters)
Note: Unless otherwise specified, tolerance = 0.05
11.00 ?0.1 B
0.10 C
(4x)
1.60 ?0.10
A1 C O R N ER I D EX AR EA N
2.80 ?0.10
+
7.0 ?0.1
A
+
0.74 ?0.06 0.35 ?0.05 8.80 B S C 0.1 C 0 S eati ng Pl ane C 0.1 C
1.20 M AX
L 8 7 6 5 4 3 2 1
K
J
I
H
G
F
E
D
C
B
A
+
5.60 B S C
0.80 TY P
0.45 ?0.05 ?0.15 M ?0.08 M CAB C
Pi A1 n I ex M ark nd
+
r1.3/May 02
42
HY29LV320
ORDERING INFORMATION Hynix products are available in several speeds, packages and operating temperature ranges. The ordering part number is formed by combining a number of fields, as indicated below. Refer to the `Valid Combinations' table, which lists the configurations that are planned to be supported in volume. Please contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29LV320 X X X X X SPECIAL INSTRUCTIONS TEMPERATURE RANGE Blank = Commercial ( 0 to +70 C) I = Industrial (-40 to +85 C) SPEED OPTION 70 80 90 12 PACKAGE TYPE T = 48-Pin Thin Small Outline Package (TSOP) F = 63-Ball Fine-Pitch Ball Grid Array (FBGA), 7.0 x 11 mm BOOT BLOCK LOCATION T = Top Boot Block Option B = Bottom Boot Block Option DEVICE NUMBER HY29LV320 = 32 Megabit (2M x 16) CMOS 3 Volt-Only Sector Erase Flash Memory = = = = 70 ns 80 ns 90 ns 120 ns
VALID COMBINATIONS
P ackag e an d S p eed FBGA Temperature Commercial Industrial Commercial 70 n s -F-70I F-70 80 n s F-80 F-80I -90 n s 120 n s 70 n s Operating Voltage: 2.7 - 3.6 Volts F-90 F-12 -T-80 F-90I F-12I T-70I T-80I Operating Voltage: 3.0 - 3.6 Volts --T-70 -T-90 T-90I -T-12 T-12I -TSOP 80 n s 90 n s 120 n s
Note: 1. The complete part number is formed by appending the suffix shown in the table to the Device Number. For example, the part number for a 90 ns, Industrial temperature range device in the TSOP package with the top boot block option is HY29LV320TT-90I.
r1.3/May 02
43
HY29LV320 Important Notice
(c) 2001 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collectively "Hynix"). The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Conditions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose. Hynix's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Hynix prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
R evision R ecord R ev.
1.0
D ate
4/01 Ori gi nal i ssue.
D etails
-70 operati ng voltage speci fi cati on changed to 2.7 - 3.6V for Industri al temperature grade. C hanged WP#/AC C i nput rqui rement to VIH duri ng sector group protect/unprotect operati ons. C hanged sector and chi p erase parameters and correspondi ng C FI data. C orrected Fi gure 22 and error i n T ble 9. a ILIT (Input Load C urrent) spec for WP#/AC C pi n eli mi nated. FBGA package spec changed from 48ball(12x7.25mm) wi th 0.3ball di ameter to 63ball(11x7mm2) wi th 0.45 ball di ameter for better reli abi li ty.
1.1
7/01
1.3
5/02
Memory Sales and Marketing Division Hynix Semiconductor Inc. 10 Fl., Hynix Youngdong Building 891, Daechi-dong, Kangnam-gu Seoul, Korea Telephone: +82-2-3459-5980 Fax: +82-2-3459-5988 http://www.hynix.com
Flash Memory Business Unit Hynix Semiconductor America Inc. 3101 North First Street San Jose, CA 95134 USA Telephone: (408) 232-8800 Fax: (408) 232-8805 http://www.us.hynix.com
44
r1.3/May 02

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